1. Field of the Invention
The present invention relates to a network device for processing data in a network and more particularly to architectural layout for the network device that allows for enhanced processing speeds as well as expandability.
2. Description of the Related Art
A network may include one or more network devices, such as Ethernet switches, each of which includes several modules that are used to process information that is transmitted through the device. Specifically, the device may include port interface modules, designed to send and receive data over a network, a Memory Management Unit (MMU), to store that data until it is forwarded or further processed and resolution modules, that allow the data to be reviewed and processed according to instructions. The resolution modules include switching functionalities for determining to which destination port data should be directed. One of the ports on the network device may be a CPU port that enables the device to send and receive information to and from external switching/routing control entities or CPUs.
Many network devices operate as Ethernet switches, where packets enter the device from multiple ports, where switching and other processing are performed on the packets. Thereafter, the packets are transmitted to one or more destination ports through the MMU. The MMU enables sharing of packet buffer among different ports while providing resource guarantees for every ingress port, egress port and class of service queue. However, many of these prior art network devices are not expandable and if a user selects such prior art network devices to coordinate and direct traffic on a network, there are serious design constraints that must be accepted or worked around.